/*
 * mdio = ~feff aka 0x100 aka gpio2
 * mdc = ~ff7f aka 0x80 aka gpio1
*/

#define	GPIO_REG	ADM8668_WAN_BASE + 0x5c

/* GPIO reg is single word. looks like:
 * 32bit: 0 000??? 000ccc 0 000ddd 000ooo 000iii
 * i guess. one would think this would have room for 6, not just 3 gpios...
 * c = change (like, irq bit)
 * d = direction, 1=out
 * o = output value
 * i = input value
 */

#define	GPIO_IN(x)	(1 << x)
#define GPIO_OUT(x)	((1 << 6) << x)
#define GPIO_DIR(x)	((1 << 12) << x)

gpio_init
{
	GPIO_REG |= (GPIO1_OUTPUT_EN|GPIO2_OUTPUT_EN)
	GPIO_SET(1)
}

ifx_mdio_mode(out)
{
	if (out)
 		GPIO_REG |= GPIO2_OUTPUT_EN
	else
		GPIO_REG &= ~GPIO2_OUTPUT_EN
}

ifx_sw_mdio_readbit
{
  return (GPIO_REG & 0x4) >> 2;
}

ifx_mdio_lo
{
  GPIO_CLR(1)
}

ifx_mdc_lo
{
  GPIO_CLR(2)
}

ifx_mdc_hi
{
	GPIO_SET(2)
}

ifx_mdio_hi
{
	GPIO_SET(1)
}

ifx_sw_read
{
	u64 i;

	ifx_gpio_init();

	/* for (i = 0x20c49d * loops_per_jiffy; i; i--) ; */

	udelay(215);
	ifx_mdc_lo();
	ifx_mdio_lo();
	udelay(215);

	/* send preamble */
	ifx_mdio_hi();
	for (i = 0; i < 32; i++)
		ifx_sw_mdc_pulse();
    ...
}